The ability to fabricate Complementary Metal Oxide Semiconductor (CMOS) circuits has spawned a new generation of integrated circuits. The CMOS technology has made possible the integration of more circuits onto a smaller substrate space.
The principal advantage of the CMOS technology is the use of N-channel and P-channel devices for their complementary characteristics. According to current CMOS fabrication techniques, lateral P-channel and N-channel transistors are formed adjacently in the semiconductor substrate. As the basis for forming these two different types of devices, a P-well and an N-well of semiconductor material are formed in the semiconductor substrate. In addition, the P+ source and drain regions of the PMOS device are formed in the N-well while a corresponding pair of N+ regions are formed in the P-well to provide the NMOS device.
It can be seen that in the CMOS structure there exists a number of lateral P and N junctions which are known to have the characteristics of a SCR type of device. Under certain conditions, sufficient charged particles may flow between the junctions of the so-called parasitic SCR-like device and latch it into a conductive state. It is apparent that when the parasitic SCR device becomes latched, the CMOS circuit is unable to function properly.
The scaling down of CMOS circuits to further miniaturize CMOS transistors and conserve substrate space aggravates the problem of latch-up. In scaling CMOS integrated circuits, the spacing between semiconductor regions is made smaller so that more integrated circuits can occupy a given substrate space. However, because of the closer spacing between various P and N junctions, the parasitic gain increases. Accordingly, the lifetime of the charged particles is such that there is an increased probability of crossing a junction and thereby initiating the triggering of the parasitic SCR.
Various approaches have been taken to circumvent the problem of latch-up in CMOS circuits. Trenches have been used, for example, for separating the P-channel and N-channel devices in an attempt to reduce the gain of the lateral parasitic SCR. Resort has also been had to epitaxial slices to reduce the voltage buildup on the parasitic junctions. Retrograded wells of semiconductor material having a reverse gradient doping level have been employed in an attempt to reduce the carrier lifetime of the charges. In addition, vertically stacked semiconductor structures have been fabricated to physically separate the P-channel and N-channel devices.
While these approaches have had an affect in reducing latch-up in CMOS circuits, a need still exists for providing a structure which is essentially free of the inherent latch-up phenomenon. A concomitant need also exists for a method of fabricating a latch-up free CMOS circuit using conventional technology.